可编程逻辑器件适航标准-DO254 VHDL编码规范

由 judy 提交于周三, 17 七月 2024 - 16:30

本文转载自：<a href="https://mp.weixin.qq.com/s/r-ROjpCPqqbo1-Xr5GieXw">FPGA技术联盟微信公众号</a></s…;

<table width="100%" border="1">
<tbody>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:0">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:0.td@@0" width="19.5200%">Name</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:0.td@@1" width="15.9100%">Phase</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:0.td@@2" width="64.5700%">Title</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:1">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:1.td@@0" width="19.5200%">DO254_VHDL.1122</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:1.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:1.td@@2" width="64.5700%">Avoid assigning a signal multiple times in the same sequential path. 
避免同一时序路径下对一个信号进行多次赋值</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:2">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:2.td@@0" width="19.5200%">DO254_NETLIST.1141</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:2.td@@1" width="15.9100%">Chip</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:2.td@@2" width="64.5700%">Do not overload a wire with too many drivers. 
禁止对同一信号线进行多源驱动</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:3">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:3.td@@0" width="19.5200%">DO254_NETLIST.1142</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:3.td@@1" width="15.9100%">Constraints general</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:3.td@@2" width="64.5700%">Do not have simultaneously active drivers on one signal.
同一个信号禁止同时有两个及以上有效驱动器</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:4">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:4.td@@0" width="19.5200%">DO254_NETLIST.1143_a</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:4.td@@1" width="15.9100%">Chip</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:4.td@@2" width="64.5700%">Use tri-states to control bidirectional bus mode. 
使用三态控制双向总线</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:5">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:5.td@@0" width="19.5200%">DO254_NETLIST.1143_b</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:5.td@@1" width="15.9100%">Chip</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:5.td@@2" width="64.5700%">Only tri-state elements should be connected to the bidirectional buses.
只有三态逻辑可连接到双向总线上</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:6">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:6.td@@0" width="19.5200%">DO254_NETLIST.1211</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:6.td@@1" width="15.9100%">Constraints clocks</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:6.td@@2" width="64.5700%">Do not use gated clocks (FPGA). 不适用门控时钟（FPGA）</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:7">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:7.td@@0" width="19.5200%">DO254_NETLIST.1212_a</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:7.td@@1" width="15.9100%">Constraints clocks</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:7.td@@2" width="64.5700%">Isolate gated clocks to a separate clock generator instance. 
门控时钟应独立设计为一个时钟生成模块</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:8">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:8.td@@0" width="19.5200%">DO254_NETLIST.1212_b</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:8.td@@1" width="15.9100%">Constraints clocks</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:8.td@@2" width="64.5700%">Gated clocks can be used only at top level (ASIC). 
只能在顶层使用门控时钟（ASIC）</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:9">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:9.td@@0" width="19.5200%">DO254_NETLIST.1221</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:9.td@@1" width="15.9100%">Constraints clocks</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:9.td@@2" width="64.5700%">Do not use flip-flop output as a clock. 
不将触发器的输出作为时钟使用</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:10">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:10.td@@0" width="19.5200%">DO254_NETLIST.1222</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:10.td@@1" width="15.9100%">Constraints clocks</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:10.td@@2" width="64.5700%">Do not connect clocks to anything other than flip-flop clock pins. 
仅将时钟信号连接到触发器的时钟引脚</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:11">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:11.td@@0" width="19.5200%">DO254_NETLIST.1231</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:11.td@@1" width="15.9100%">Constraints resets</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:11.td@@2" width="64.5700%">Do not connect resets to anything other than flip-flop reset pins.
仅将复位信号连接至触发器的复位引脚</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:12">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:12.td@@0" width="19.5200%">DO254_NETLIST.1232_a</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:12.td@@1" width="15.9100%">Chip</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:12.td@@2" width="64.5700%">Do not use combinatorial logic in reset lines. 
复位信号链路中不使用组合逻辑</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:13">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:13.td@@0" width="19.5200%">DO254_NETLIST.1232_b</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:13.td@@1" width="15.9100%">Constraints resets</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:13.td@@2" width="64.5700%">Avoid internally generated resets.避免使用内部产生的复位信号</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:14">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:14.td@@0" width="19.5200%">DO254_NETLIST.1232_c</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:14.td@@1" width="15.9100%">Constraints resets</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:14.td@@2" width="64.5700%">Place the reset generator instance at the top-level of design hierarchy.在顶层例化复位信号产生模块</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:15">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:15.td@@0" width="19.5200%">DO254_NETLIST.1242</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:15.td@@1" width="15.9100%">Constraints resets</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:15.td@@2" width="64.5700%">A flip-flop inference should have one asynchronous control. 
触发器应具有异步控制端口</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:16">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:16.td@@0" width="19.5200%">DO254_NETLIST.1243</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:16.td@@1" width="15.9100%">Constraints resets</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:16.td@@2" width="64.5700%">Do not use the same signal as clock and reset. 
不将一个信号同时用做时钟信号和复位信号</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:17">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:17.td@@0" width="19.5200%">DO254_NETLIST.1244</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:17.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:17.td@@2" width="64.5700%">Do not use resets with mixed polarity. 
复位信号使用单一极性</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:18">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:18.td@@0" width="19.5200%">DO254_NETLIST.1245</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:18.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:18.td@@2" width="64.5700%">All registers should have a reset control. 
所有寄存器都应具有复位控制端口</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:19">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:19.td@@0" width="19.5200%">DO254_VHDL.1311</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:19.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:19.td@@2" width="64.5700%">Use the 'std_logic_1164' standard package whenever it is possible.
 尽量使用‘std_logic_1164’库</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:20">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:20.td@@0" width="19.5200%">DO254_VHDL.1312</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:20.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:20.td@@2" width="64.5700%">Use the 'numeric_std' package instead of 'std_logic_arith' and 'std_logic_unsigned' packages.
 使用'numeric_std'尽量不使用'std_logic_arith' 和 'std_logic_unsigned'</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:21">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:21.td@@0" width="19.5200%">DO254_VHDL.1313</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:21.td@@1" width="15.9100%">Elaboration</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:21.td@@2" width="64.5700%">Use 'std_logic' only for I/O ports.仅对I/O端口使用 'std_logic'</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:22">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:22.td@@0" width="19.5200%">DO254_VHDL.1314</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:22.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:22.td@@2" width="64.5700%">Do not use unsafe data types inside architecture. 
在结构体不使用不安全的数据类型</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:23">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:23.td@@0" width="19.5200%">DO254_VHDL.1315</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:23.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:23.td@@2" width="64.5700%">Specify range for objects of 'integer' data type.'integer'
数据类型对象须声明范围</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:24">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:24.td@@0" width="19.5200%">DO254_VHDL.1316</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:24.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:24.td@@2" width="64.5700%">Do not use the 'bit' data type.
禁止使用 'bit'数据类型</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:25">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:25.td@@0" width="19.5200%">DO254_VHDL.1317</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:25.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:25.td@@2" width="64.5700%">Do not use the 'enum_encoding' attribute for enumerations. 
枚举对象禁止使用'enum_encoding'属性</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:26">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:26.td@@0" width="19.5200%">DO254_VHDL.1318</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:26.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:26.td@@2" width="64.5700%">Specify range for interface objects of 'std_logic_vector' data type.' std_logic_vector '
数据类型对象须声明位宽</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:27">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:27.td@@0" width="19.5200%">DO254_VHDL.1321</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:27.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:27.td@@2" width="64.5700%">Use descending range for one-dimensional objects. 
使用降序声明一维数据对象的范围</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:28">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:28.td@@0" width="19.5200%">DO254_VHDL.1322</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:28.td@@1" width="15.9100%">Elaboration</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:28.td@@2" width="64.5700%">Specify '0' as least significant bit for one-dimensional objects. 
使用‘0’表示一维数据对象的最低位</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:29">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:29.td@@0" width="19.5200%">DO254_VHDL.1323</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:29.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:29.td@@2" width="64.5700%">Use simple signals only for non-constant indexing. 
数据的非常量索引应使用简单的信号表示（索引不能使用表达式）</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:30">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:30.td@@0" width="19.5200%">DO254_VHDL.1331</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:30.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:30.td@@2" width="64.5700%">All declared objects should be used in the description. 
声明的所有对象都应被使用</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:31">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:31.td@@0" width="19.5200%">DO254_VHDL.1332</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:31.td@@1" width="15.9100%">Elaboration</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:31.td@@2" width="64.5700%">All declared signals should be used in the description.
 声明的所有信号都应被使用</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:32">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:32.td@@0" width="19.5200%">DO254_VHDL.1341</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:32.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:32.td@@2" width="64.5700%">Use constants or generics instead of hard-coded numbers. 
使用常量或者参量代替数字</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:33">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:33.td@@0" width="19.5200%">DO254_VHDL.1342</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:33.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:33.td@@2" width="64.5700%">Avoid Hard-Coded vector reset Assignments.
 避免在复位中直接使用数字矢量（将复位值定义为常量或者参量）</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:34">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:34.td@@0" width="19.5200%">DO254_VHDL.1411</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:34.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:34.td@@2" width="64.5700%">Do not use ordered port connections.
 端口映射禁止使用顺序映射</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:35">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:35.td@@0" width="19.5200%">DO254_VHDL.1412</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:35.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:35.td@@2" width="64.5700%">Match port and connected signal names. 
匹配信号名称及所连接的端口名称</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:36">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:36.td@@0" width="19.5200%">DO254_VHDL.1421</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:36.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:36.td@@2" width="64.5700%">Avoid unconnected input ports in component instance. 
例化时，避免模块输入端口悬空</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:37">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:37.td@@0" width="19.5200%">DO254_VHDL.1422</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:37.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:37.td@@2" width="64.5700%">Avoid unconnected output ports in component instance. 
例化时，避免模块输出端口悬空</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:38">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:38.td@@0" width="19.5200%">DO254_NETLIST.1511</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:38.td@@1" width="15.9100%">Constraints clocks</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:38.td@@2" width="64.5700%">Do not use a clock signal as a data.禁止将时钟信号用为数据</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:39">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:39.td@@0" width="19.5200%">DO254_VHDL.1615</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:39.td@@1" width="15.9100%">Elaboration</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:39.td@@2" width="64.5700%">Avoid mismatching in assignment ranges. 
避免赋值两端范围不匹配</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:40">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:40.td@@0" width="19.5200%">DO254_VHDL.1621</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:40.td@@1" width="15.9100%">Elaboration</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:40.td@@2" width="64.5700%">Match bit widths of relational operator arguments. 
条件运算符两边的数据位宽应匹配</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:41">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:41.td@@0" width="19.5200%">DO254_VHDL.1633</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:41.td@@1" width="15.9100%">Elaboration</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:41.td@@2" width="64.5700%">Bit widths of component port and bind signal should match. 
例化时，信号及其连接的端口数据位宽应匹配</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:42">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:42.td@@0" width="19.5200%">DO254_VHDL.1711</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:42.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:42.td@@2" width="64.5700%">Define all the necessary signals in the sensitivity list. 
敏感列表包含所有必需的信号</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:43">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:43.td@@0" width="19.5200%">DO254_VHDL.1721</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:43.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:43.td@@2" width="64.5700%">Do not define unnecessary objects in the sensitivity list. 
禁止敏感列表中包含非必需的信号</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:44">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:44.td@@0" width="19.5200%">DO254_VHDL.1722</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:44.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:44.td@@2" width="64.5700%">Do not use a signal within the same process statement it was assigned.
 不在信号赋值的过程中使用该信号</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:45">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:45.td@@0" width="19.5200%">DO254_VHDL.1811</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:45.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:45.td@@2" width="64.5700%">Do not read global signals in a function body.
函数中不适用全局信号</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:46">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:46.td@@0" width="19.5200%">DO254_VHDL.1812</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:46.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:46.td@@2" width="64.5700%">Function return value should be defined in all the possible cases. 
函数的返回值在任何条件下都应是确定的</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:47">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:47.td@@0" width="19.5200%">DO254_VHDL.1821</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:47.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:47.td@@2" width="64.5700%">A function should return at the end of its body. 
函数应在其函数体的结尾处返回</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:48">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:48.td@@0" width="19.5200%">DO254_VHDL.1822</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:48.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:48.td@@2" width="64.5700%">Function should not return in conditional branches. 
禁止函数在条件语句分支中返回</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:49">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:49.td@@0" width="19.5200%">DO254_VHDL.1911</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:49.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:49.td@@2" width="64.5700%">Use proper encoding type for FSM states. 
有限状态机使用合适的编码</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:50">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:50.td@@0" width="19.5200%">DO254_VHDL.1912</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:50.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:50.td@@2" width="64.5700%">Use constants to define FSM state vectors. 
使用常量定义有限状态机的向量</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:51">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:51.td@@0" width="19.5200%">DO254_VHDL.1921</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:51.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:51.td@@2" width="64.5700%">Each FSM should have reset control. 
每一个有限状态机都应具有复位控制</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:52">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:52.td@@0" width="19.5200%">DO254_VHDL.1922</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:52.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:52.td@@2" width="64.5700%">All illegal or undefined states should transition to a defined state in a case of state corruption. 
有限状态机应具备从非法或未定义状态中自动跳转到定义的状态中</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:53">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:53.td@@0" width="19.5200%">DO254_VHDL.1923</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:53.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:53.td@@2" width="64.5700%">Avoid unreachable states in FSM descriptions. 
避免有限状态机中包含不可达状态</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:54">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:54.td@@0" width="19.5200%">DO254_VHDL.1924</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:54.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:54.td@@2" width="64.5700%">Avoid deadlock states in FSM descriptions. 
避免有限状态机中死锁状态</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:55">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:55.td@@0" width="19.5200%">DO254_NETLIST.1925</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:55.td@@1" width="15.9100%">Chip</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:55.td@@2" width="64.5700%">All FSM inputs should be synchronous to the state machine clock. 
所有有限状态机的输入都应利用其主时钟进行同步后使用</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:56">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:56.td@@0" width="19.5200%">DO254_NETLIST.2112</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:56.td@@1" width="15.9100%">Chip</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:56.td@@2" width="64.5700%">Port description order should follow a pattern. 
端口定义顺序应服从某一模式</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:57">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:57.td@@0" width="19.5200%">DO254_VHDL.2121_a</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:57.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:57.td@@2" width="64.5700%">Do not describe multiple statements in one line.
 禁止一行中包含多条语句</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:58">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:58.td@@0" width="19.5200%">DO254_VHDL.2121_b</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:58.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:58.td@@2" width="64.5700%">Do not describe multiple association elements in one line. 
禁止一行中包含多个元素</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:59">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:59.td@@0" width="19.5200%">DO254_VHDL.2121_c</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:59.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:59.td@@2" width="64.5700%">Do not describe multiple declarations per line. 
禁止一行中包含多个声明</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:60">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:60.td@@0" width="19.5200%">DO254_VHDL.2122</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:60.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:60.td@@2" width="64.5700%">Label statements whenever it is possible. 
尽量对语句进行标识</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:61">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:61.td@@0" width="19.5200%">DO254_VHDL.2123</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:61.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:61.td@@2" width="64.5700%">Always use ending label or constructs name at the end of the statements and declarations. 
在语句和声明的结尾处使用标识</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:62">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:62.td@@0" width="19.5200%">DO254_VHDL.2124</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:62.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:62.td@@2" width="64.5700%">Do not use the same names for different objects. 
禁止对不同对象使用同一名称</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:63">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:63.td@@0" width="19.5200%">DO254_VHDL.2125</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:63.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:63.td@@2" width="64.5700%">Indent each level of the source code. 
代码逐层缩进</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:64">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:64.td@@0" width="19.5200%">DO254_VHDL.2126</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:64.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:64.td@@2" width="64.5700%">Use spaces instead of tabs. 
使用空格，而不使用占位符</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:65">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:65.td@@0" width="19.5200%">DO254_VHDL.2131</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:65.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:65.td@@2" width="64.5700%">Avoid large design files. 
避免单一设计过大</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:66">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:66.td@@0" width="19.5200%">DO254_VHDL.2132</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:66.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:66.td@@2" width="64.5700%">Describe one design unit per file.每一个设计文件仅包含一个设计模块</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:67">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:67.td@@0" width="19.5200%">DO254_VHDL.2141</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:67.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:67.td@@2" width="64.5700%">Ensure consistent file header. 
确保一致的文件头注释</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:68">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:68.td@@0" width="19.5200%">DO254_VHDL.2142</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:68.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:68.td@@2" width="64.5700%">Ensure sufficient comment density.确保充足的注释</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:69">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:69.td@@0" width="19.5200%">DO254_VHDL.2143</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:69.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:69.td@@2" width="64.5700%">Ensure commenting of design constructs. 
确保设计结构具有注释</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:70">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:70.td@@0" width="19.5200%">DO254_VHDL.2221</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:70.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:70.td@@2" width="64.5700%">Do not describe same objects using both upper and lower letter case.禁止同一对象一处使用大写，在另一处使用小写（同一对象名称应大小写保持不变）</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:71">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:71.td@@0" width="19.5200%">DO254_VHDL.3111</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:71.td@@1" width="15.9100%">Elaboration</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:71.td@@2" width="64.5700%">Do not use multiple waveform and optional delay expression in assignments. 
禁止在赋值中使用多个波形和可选的延迟表达式</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:72">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:72.td@@0" width="19.5200%">DO254_VHDL.3121</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:72.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:72.td@@2" width="64.5700%">Avoid using records in RTL description. 
禁止在寄存器传输级设计中使用records</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:73">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:73.td@@0" width="19.5200%">DO254_VHDL.3131</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:73.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:73.td@@2" width="64.5700%">Do not use register initialization assignments.
 禁止对寄存器定义时赋初值</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:74">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:74.td@@0" width="19.5200%">DO254_VHDL.3141</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:74.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:74.td@@2" width="64.5700%">Avoid Undriven Signals. 
禁止未经驱动的信号</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:75">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:75.td@@0" width="19.5200%">DO254_NETLIST.3151</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:75.td@@1" width="15.9100%">Constraints general</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:75.td@@2" width="64.5700%">Avoid long combinational paths. 
禁止长组合逻辑路径</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:76">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:76.td@@0" width="19.5200%">DO254_VHDL.3152</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:76.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:76.td@@2" width="64.5700%">Limit the use of nested 'if' and 'case' statements. 
限制if和case语句的嵌套级数</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:77">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:77.td@@0" width="19.5200%">DO254_VHDL.3212</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:77.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:77.td@@2" width="64.5700%">Case statement should always have 'others' choice. 
Case语句必须包含others分支</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:78">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:78.td@@0" width="19.5200%">DO254_VHDL.3221</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:78.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:78.td@@2" width="64.5700%">Do not describe unreachable conditions. 
禁止包含不可达条件分支</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:79">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:79.td@@0" width="19.5200%">DO254_VHDL.3223</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:79.td@@1" width="15.9100%">Parse</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:79.td@@2" width="64.5700%">Do not use 'with select' statement.禁止使用’with select’语句</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:80">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:80.td@@0" width="19.5200%">DO254_NETLIST.3411</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:80.td@@1" width="15.9100%">Chip</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:80.td@@2" width="64.5700%">Do not connect inout port directly to input/output ports. 
禁止直接将inout端口连接至input或者output端口</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:81">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:81.td@@0" width="19.5200%">DO254_NETLIST.3412</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:81.td@@1" width="15.9100%">Constraints general</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:81.td@@2" width="64.5700%">Avoid delay chains in digital logic.禁止在数字逻辑中包含延时</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:82">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:82.td@@0" width="19.5200%">DO254_NETLIST.3413</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:82.td@@1" width="15.9100%">Constraints general</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:82.td@@2" width="64.5700%">Associate each signal with only one non-tri-state driver. 
每个信号仅使用一个非三态源进行驱动</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:83">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:83.td@@0" width="19.5200%">DO254_NETLIST.3414</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:83.td@@1" width="15.9100%">Constraints general</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:83.td@@2" width="64.5700%">Avoid feed-throughs in digital logic. 
避免在数字逻辑中使用输入输出直连</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:84">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:84.td@@0" width="19.5200%">DO254_NETLIST.3511</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:84.td@@1" width="15.9100%">Constraints general</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:84.td@@2" width="64.5700%">Do not use combinatorial feedbacks.禁止使用组合逻辑反馈</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:85">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:85.td@@0" width="19.5200%">DO254_VHDL.3611</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:85.td@@1" width="15.9100%">Elaboration</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:85.td@@2" width="64.5700%">Do not describe multiple independent conditions in the process.
禁止在process中使用多个独立的条件</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:86">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:86.td@@0" width="19.5200%">DO254_NETLIST.3621</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:86.td@@1" width="15.9100%">Constraints general</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:86.td@@2" width="64.5700%">Avoid latches as much as possible.尽量避免使用锁存器</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:87">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:87.td@@0" width="19.5200%">DO254_NETLIST.3631</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:87.td@@1" width="15.9100%">Chip</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:87.td@@2" width="64.5700%">Each register should be controllable from its inputs. 
应能从外部输入引脚控制每个寄存器</td>
</tr>
<tr opera-tn-ra-comp="_$.pages:0.layers:0.comps:0.classicTable1:88">
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:88.td@@0" width="19.5200%">DO254_VHDL.3641</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:88.td@@1" width="15.9100%">Synthesis</td>
<td colspan="1" rowspan="1" opera-tn-ra-cell="_$.pages:0.layers:0.comps:0.classicTable1:88.td@@2" width="64.5700%">Avoid using variables to infer sequential logic.
 避免时序逻辑中使用变量</td>
</tr>
</tbody>
</table>